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ZEN2041F
P ROGRAMMABLE UNIVE RSAL COUNTE R
Description ZENIC ZEN2041F is a pr ogr a m m a ble u n iver sa l cou n t er LSI. TH E ZEN2041F cou n t s ph a se-sh ift ed sign a ls a n d u p/down pu lse sign a ls, gen er a t ed fr om r ot a r y en coder s or lin ea r sca les. Sin ce t h e cou n t er r espon se speed is a s h igh a s 20MH z(MAX),t h e ZEN2041F is u sed in a va r iet y of h igh speed ser vices in clu din g digit a l ser vo con t r ol a n d pr ecision m ea su r em en t . TH E ZEN2041F is pr ovided wit h a fu n ct ion wh ich m on it or s t h e in pu t sign a ls a n d det ect s a n y a bn or m a l in pu t a ccom pa n ied wit h n oise or ot h er dist u r ba n ces, so t h a t t h e r elia bilit y of cou n t ed va lu es a r e secu r ed. 1. Features Select a ble cou n t r esolu t ion a n d ch a n n els. 16bit 4ch . or 32bit 2ch . or 16bit 2ch . + 32bit 1ch . Cou n t r espon se speed: 20Mcps.(MAX.) ( CLK f0 = 20MH z a t 50% du t y) In pu t fr equ en cy of cou n t pu lse. P h a se -sh ift ed sign a l in pu t : A/B ph a se in pu t DC ~ 5MH z. (less t h a n f0 1/4) U p/down pu lse sign a l in pu t : U p/down in pu t DC ~ 10MH z (less t h a n f0 1/2) CLK fr equ en cy DC ~ 20MH z. (MAX.:du t y r a t io 50%) Dir ect ion r ecogn it ion for u p/down cou n t in g Abn or m a l in pu t det ect ion cir cu it . P r eloa d r egist er for t h e u p/down cou n t er . La t ch r egist er for t h e u p/down cou n t er . Refer en ce va lu e - cou n t va lu e coin ciden ce det ect ion fu n ct ion . On -ch ip st a t u s r egist er .
Cou n t er oper a t ion m ode. E dge eva lu a t ion select ion : 1/2/4 . (on ly for ph a se -sh ift ed sign a l in pu t ) Cou n t dir ect ion select ion . Cou n t er clea r con t r ol:syn ch r on ou s/ a syn ch r on ou s clea r . Select a ble 16/8 bit da t a bu s. Low power CMOS t ech n ology. TTL com pa t ible. Sin gle 5V power su pply. 100 pin QF P .
Typical Applications F or Mu lt i ch a n n el N C m a ch in e t ools P r ecision posit ion er s Robot a r m con t r oller s Speed con t r oller s for r ot a t in g m a ch in es E lect r on ic ga u ges F r equ en cy cou n t er s
Pin configuration (Top View)
EP3 / O3 2 E3 1 / O3 1 E3 0 / O3 0 VDD P3 0 P3 1 C3 LD3 LT3 M D3 DI R3 S1 LD2 LT2 VSS E2 0 / O2 0 E2 1 / O2 1 EP2 / O2 2 C2 VDD VSS P2 1 P2 0 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 VSS VSS VDD VDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
LT1 LD1 DI R1 M D1 EP1 / O1 2
VDD P1 0 P1 1 C1 S0 LT0 LD0 DI R0 M D0 C0
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
M D2 DI R2 D1 5 D1 4 D1 3 D1 2 D1 1 VSS VDD D1 0 D9 D8 AD5 AD4 AD3 AD2 AD1 AD0
P0 1 P0 0 VSS VDD E0 0 / O0 0 E0 1 / O0 1 EP0 / O0 2
VSS I NT RESET WB / BHE RD W R CS D0 D1 D2 D3 VDD D4 D5 D6 D7 VDD VDD VSS VSS CLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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ZEN2041F
2. Block diagram (Figure.2) AD5-0 CS WR RD IN T BH E W/B
CP U In t er fa ce
Da t a bu s bu ffer
D15-D0
Con t r ol logic
P 00 P 01 C0 LD0 LT0 MD0 DIR0 P 10 P 11 C1 LD1 LT1 MD1 DIR1 S0
Gr ou p 0 Dir ect ion r ecogn it ion
Cou n t er u n it 0 LDR CNT LTR 0 0 0
Com pa r a t or
0
CMR CMR
E 00/O00 E 01/O01 E P 0/O02
00
01
Gr ou p 1 Dir ect ion r ecogn it ion
Cou n t er u n it 1 LDR CNT LTR 1 1 1
Com pa r a t or
1
CMR CMR
E 10/O10 E 11/O11 E P 1/O12
10
11
P 20 P 21 C2 LD2 LT2 MD2 DIR2 P 30 P 31 C3 LD3 LT3 MD3 DIR3 S1 RE SE T CLK VDD VSS
Gr ou p 2 Dir ect ion r ecogn it ion
Cou n t er u n it 2 LDR CNT LTR 2 2 2
Com pa r a t or
2
CMR CMR
E 20/O20 E 21/O21 E P 2/O22
20
21
Gr ou p 3 Dir ect ion r ecogn it ion
Cou n t er u n it 3 LDR CNT LTR 3 3 3
Com pa r a t or
2
CMR CMR
E 30/O30 E 31/O31 E P 3/O32
30
31
LDR CN T LTR CMR
:P r eloa d Regist er :U p/down Cou n t er :La t ch Regist er :Refer en ce Regist er
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ZEN2041F
3. Block Description (refer to Figure.2) 1) CP U In t er fa ce It is in t er fa ce t o wr it e da t a in t o r egist er or r ea d da t a fr om r egist er . It ou t pu t s t h e IN T sign a l by in t er r u pt fr om dir ect ion r ecogn it ion logic a n d com pa r a t or . Refer t o [5.Ba sic Oper a t ion s] a n d [6.In t er n a l Regist er Ma ppin g]. 2) Con t r ol logic It oper a t es t o wr it e da t a in t o r egist er or r ea d da t a fr om r egist er . It t r a n sm it s in t er r u pt sign a l t o CP U in t er fa ce fr om dir ect ion r ecogn it ion logic a n d com pa r a t or . 3) Da t a Bu s Bu ffer It is 16 or 8bit bidir ect ion a l, a n d in t er fa ce bet ween CP U a n d ZEN2041F. 4) Dir ect ion Recogn it ion It ou t pu t s t h e U P , DOWN , Da t a Loa d a n d Da t a La t ch sign a l t o t h e cou n t er u pon t h e ext er n a l sign a l, m ode r egist er , com m a n d r egist er . If in t er r u pt en a ble, it in dica t es CP U in t er fa ce t o m a ke IN T="L". Th e in pu t sign a ls ca n be m on it or ed by t h e m on it or r egist er , t h er efor e t h e in pu t sign a ls(*) n ot in pu t ed t o t h e cou n t er ca n be u sed for u n iver sa l in pu t s. 5) Cou n t er u n it It is com posed of t h e loa d r egist er , u p/down cou n t er a n d com m a n d r egist er . It oper a t es by t h e U P , DOWN , CLE AR, DATA LOAD, DATA LATCH , a n d Ca r r y, Bor r ow. Th e cou n t er con n ect ion S0 a n d S1 det er m in e t h e dir ect ion r ecogn it ion gr ou p a n d t h e pr e-st a ge cou n t er . S0 Con n ect ion 0 1 In depen den t Ca sca de Cou n t er u n it 0 1 0 1 Dir ect ion Recogn it ion Gr ou p 0 1 0 0 P r e-st a ge Cou n t er u n it 0
Cou n t er Dir ect ion P r e-st a ge u n it Recogn it ion Cou n t er u n it 0 In depen den t 2 Gr ou p 2 3 3 1 Ca sca de 2 2 3 2 2 Ca sca de con n ect ion ( 32bit cou n t er ) Cou n t er u n it 0 a n d 2 a r e lower wor d(16bit ). An d, cou n t er u n it 1 a n d 3 a r e u pper wor d(16bit ). 6) Com pa r a t or It is com posed of t wo r efer en ce r egist er s. It com pa r es t h e cou n t er va lu e wit h t h e r efer en ce r egist er . If t h e coin ciden ce is det ect ed, com pa r a t or ou t pu t s t h e st a t u s, t h e in t er r u pt , t h e coin ciden ce a n d t h e win dow, a ccor din g t o t h e set t in g con dit ion . Refer t o [9.Coin ciden ce Det ect ion F u n ct ion ].
S1 Con n ect ion
*)In pu t sign a ls t o t h e gr ou p 1 a n d 3 wh en ca sca de con n ect ed.
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ZEN2041F
4. Pin Definitions and Functions P in Sym bol 36 AD5 35 AD4 34 AD3 33 AD2 32 AD1 31 AD0 16 CS 14 RD 15 WR 10 IN T 12 W/B 13 BH E 46 D15 45 D14 44 D13 43 D12 42 D11 39 D10 38 D9 37 D8 25 D7 24 D6 23 D5 22 D4 20 D3 19 D2 18 D1 17 D0 11 RESET 30 CLK 2 P 00 1 P 01 91 P 10 92 P 11 51 P 20 52 P 21 70 P 30 69 P 31 100 C0 93 C1 55 C2 68 C3 97 LD0 83 LD1 61 LD2 67 LD3 96 LT0 82 LT1 60 LT2 66 LT3 I/O Ta ble.1 F u n ct ion s Addr ess0-5 Th ese a r e u sed for select ion in t er n a l r egist er wit h W/B a n d BH E . Refer t o [5.Ba sic Oper a t ion s] a n d [6.In t er n a l Regist er Ma ppin g].
I
I I I O I I
CH IP SE LE CT RE AD WRITE IN E RRU P T RE QU E ST WORD/BYTE : Wor d t r a n sfer is "H ". Byt e t r a n sfer is "L". BU S H IGH E N ABLE DATA BUS E n a ble bit s a r e select ed by BH E a n d AD0. Refer t o [5.Ba sic Oper a t ion s.].
I/O
I I
RE SE T:in it ia lize in t er n a l r egist er s. CLOCK:is u sed for syn ch r on izin g in t er n a l sign a ls a n d cou n t in g. P U LSE IN P U TS 00-31 Refer t o [8. Cou n t er Oper a t ion a n d Tim in g.].
I
I
CLE AR0-3 : clea r ea ch cou n t er va lu e. Abou t clea r con dit ion s, r efer t o [7.5) Mode Regist er .].
I
DATA LOAD : Aft er t h e fa llin g edge is det ect ed, t h e va lu e of loa d r egist er is st or ed t o ea ch cou n t er .
I
DATA LATCH : Aft er t h e fa llin g edge is det ect ed, t h e va lu e of cou n t er is st or ed t o ea ch la t ch r egist er .
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ZEN2041F
P in 99 85 50 65 98 84 49 64 94 63 5 6 58 57 88 87 72 73 7 86 56 74 4 21 26 27 40 54 71 76 77 90 3 9 28 29 41 53 59 78 79 89 Sym bol I/O MD0 MD1 I MD2 MD3 DIR0 DIR1 I DIR2 DIR3 S0 I S1
E00/O00 E01/O01 E20/O20 E21/O21 E10/O10 E11/O11 E30/O30 E31/O31 EP0/O02 EP1/O12 EP2/O22 EP3/O32
F u n ct ion s MODE SE LE CTION : O : P h a se-sh ift ed pu lse 1 : U p/Down pu lse COU N TIN G DIRE CTION Refer t o [8. Cou n t in g Oper a t ion a n d Tim in g.].
COU N TE R CON N E CTION Refer t o [3.5) Cou n t er u n it ]. COIN CIDE N CE DE TE CTION 00-31 / U N IVE RSAL OU TP U T 00-31 Refer t o [9. Coin ciden ce Det ect ion F u n ct ion .].
O
O
WINDOW OUTP UT 0-3 / U NIVE RSAL OU TP U T 02-32 Refer t o [9. Coin ciden ce Det ect ion F u n ct ion .].
Su pply volt a ge +5V
VDD
-
Gr ou n d 0V
VSS
-
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ZEN2041F
5. Basic Operation CS W/B BHE AD0 RD WR D15-D8 D7-D0 1 * * * * H igh -im peda n ce H igh -im peda n ce 0 1 1 1 * * 0 1 0 0 1 0 In pu t In pu t 0 1 0 0 0 1 Ou t pu t Ou t pu t 0 1 1 0 1 0 H igh -im peda n ce In pu t 0 1 1 0 0 1 H igh -im peda n ce Ou t pu t 0 1 0 1 1 0 In pu t H igh -im peda n ce 0 1 0 1 0 1 Ou t pu t H igh -im peda n ce 0 0 1 0 1 0 H igh -im peda n ce In pu t 0 0 1 0 0 1 H igh -im peda n ce Ou t pu t 0 0 1 1 1 0 H igh -im peda n ce In pu t 0 0 1 1 0 1 H igh -im peda n ce Ou t pu t 0 0 0 * * * 0 * * * 0 0 6. Internal Register Mapping Ta ble.3 RD WR AD5 AD4 AD3 AD2 AD1 AD0 Select ed r egist er a n d Oper a t ion 1 0 0 0 0 0 0 0 Loa d r egist er 0, Wr it e 1 0 0 0 0 0 1 0 Refer en ce r egist er 00, Wr it e 1 0 0 0 0 1 0 0 Refer en ce r egist er 01, Wr it e 1 0 0 0 0 1 1 0 Mode r egist er 0, Wr it e 1 0 0 0 1 0 0 0 Loa d r egist er 1, Wr it e 1 0 0 0 1 0 1 0 Refer en ce r egist er 10, Wr it e 1 0 0 0 1 1 0 0 Refer en ce r esist er 11, Wr it e 1 0 0 0 1 1 1 0 Mode r egist er 1, Wr it e 1 0 0 1 0 0 0 0 Loa d r egist er 2, Wr it e 1 0 0 1 0 0 1 0 Refer en ce r egist er 20, Wr it e 1 0 0 1 0 1 0 0 Refer en ce r egist er 21, Wr it e 1 0 0 1 0 1 1 0 Mode r egist er 2, Wr it e 1 0 0 1 1 0 0 0 Loa d r egist er 3, Wr it e 1 0 0 1 1 0 1 0 Refer en ce r egist er 30, Wr it e 1 0 0 1 1 1 0 0 Refer en ce r egist er 31, Wr it e 1 0 0 1 1 1 1 0 Mode r egist er 3, Wr it e 1 0 1 0 0 0 0 0 Com m a n d r egist er 0, Wr it e 1 0 1 0 0 0 1 0 Com m a n d r egist er 1, Wr it e 1 0 1 0 0 1 0 0 Com m a n d r egist er 2, Wr it e 1 0 1 0 0 1 1 0 Com m a n d r egist er 3, Wr it e 1 0 1 0 1 0 0 0 Globa l com m a n d r egist er ,Wr it e 0 1 0 0 0 0 0 0 La t ch r egist er 0, Rea d 0 1 0 0 0 1 1 0 Mon it or r egist er 0, Rea d 0 1 0 0 1 0 0 0 La t ch r egist er 1, Rea d 0 1 0 0 1 1 1 0 Mon it or r egist er 1, Rea d 0 1 0 1 0 0 0 0 La t ch r egist er 2, Rea d 0 1 0 1 0 1 1 0 Mon it or r egist er 2, Rea d 0 1 0 1 1 0 0 0 La t ch r egist er 3, Rea d 0 1 0 1 1 1 1 0 Mon it or r egist er 3, Rea d 0 1 1 0 0 0 0 0 St a t u s r egist er 0, Rea d 0 1 1 0 0 0 1 0 St a t u s r egist er 1, Rea d 0 1 1 0 0 1 0 0 St a t u s r egist er 2, Rea d 0 1 1 0 0 1 1 0 St a t u s r egist er 3, Rea d (Z2041B98)ZENIC Inc. -6Ta ble.2 Ba sic Oper a t ion Disa ble Wr it e wor d da t a Rea d wor d da t a Wr it e lower byt e da t a Rea d lower byt e da t a Wr it e u pper byt e da t a Rea d u pper byt e da t a Wr it e lower byt e da t a Rea d lower byt e da t a Wr it e u pper byt e da t a Rea d u pper byt e da t a In h ibit
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ZEN2041F
7. Registers 1) Loa d r egist er Th e va lu e of t h is r egist er is st or ed in t h e u p/down cou n t er a t t h e fa llin g edge of LDn or execu t in g da t a loa d(D9) of t h e com m a n d r egist er . 2) Refer en ce r egist er n 0 Th e lower va lu e of win dow com pa r ison is st or ed in it . 3) Refer en ce r egist er n 1 Th e u pper va lu e of win dow com pa r ison is st or ed in it . 4) La t ch r egist er Th e va lu e of t h e u p/down cou n t er is st or ed in t h is r egist er a t t h e r isin g edge of LTn or execu t in g da t a la t ch (D8) of t h e com m a n d r egist er . Th ese r egist er s Digit 0(D0 ) : LSB Digit 15(D15) : MSB 5) Mode r egist er : Su bscr ipt n is 0 t o 3. Ta ble.5 Bit Sym bol D15 ILDn Descr ipt ion In t er r u pt con t r ol(LDn ) 0 : in h ibit 1 : en a ble wh en t h e D9 of m ode r egist er is "1". In t er r u pt con t r ol(LTn ) 0 : in h ibit 1 : en a ble wh en t h e D8 of m ode r egist er is "1". In t er r u pt con t r ol ( by a n a bn or m a l in pu t ) 0 : in h ibit 1 : en a ble In t er r u pt con t r ol ( by Cn ) 0 : in h ibit 1 : en a ble wh en ZE n 1="1" In t er r u pt con t r ol ( by coin ciden ce det ect ion ) 0 : in h ibit 1 : en a ble wh en E n 1="L" In t er r u pt con t r ol ( by coin ciden ce det ect ion ) 0 : in h ibit 1 : en a ble wh en E n 0="L" E n a ble LDn 0 : disa ble 1 : en a ble E n a ble LTn 0 : disa ble 1 : en a ble Ou t pu t con t r ol 2 0 : E P n /On 2 = u n iver sa l ou t pu t 1: = coin ciden ce ou t pu t Ou t pu t con t r ol 1 0 : E n 1/On 1 = u n iver sa l ou t pu t 1: = coin ciden ce ou t pu t
D14
ILTn
D13
IAIn
D12
ICn
D11
IE n 1
D10
IE n 0
D9
E LDn
D8
E LTn
D7
OCn 2
D6
OCn 1
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ZEN2041F
Bit Sym bol D5 OCn 0 Descr ipt ion Ou t pu t con t r ol 0 0 : E n 0/On 0 = u n iver sa l ou t pu t 1: = coin ciden ce ou t pu t Clea r m ode 0 : a syn ch r on ou s clea r 1 : syn ch r on ou s clea r for ph ese-sh ift ed pu lse in pu t Clea r cou n t ZE n 1 ZE n 0 0 0 n o oper a t ion 0 1 Disa ble clea r 1 0 on ly 1 t im e 1 1 ever y t im es E dge eva lu a t ion for ph a se-sh ift ed pu lse in pu t Xn 1 Xn 0 E dge eva lu a t ion 0 0 Sin gle 0 1 Dou ble 1 1 Qu a d
D4
ZMDn
D3 D2
ZE n 1 ZE n 0
D1 D0
Xn 1 Xn 0
6) Com m a n d r egist er : Su bscr ipt n is 0 t o 3. Ta ble.6 Bit Sym bol D15 RLDn Descr ipt ion Reset in t er r u pt by LDn 0 : n o oper a t ion 1 : Reset Reset in t er r u pt by LTn 0 : n o oper a t ion 1 : Reset Reset in t er r u pt by a bn or m a l in pu t 0 : n o oper a t ion 1 : Reset Reset in t er r u pt by Cn 0 : n o oper a t ion 1 : Reset Reset in t er r u pt by coin ciden ce det ect ion 0 : n o oper a t ion (D11 of m ode r egist er ) 1 : Reset Reset in t er r u pt by coin ciden ce det ect ion 0 : n o oper a t ion (D10 of m ode r egist er ) 1 : Reset Da t a loa d Wh en LDn =1, t h e va lu e of loa d r egist er is st or ed in t o t h e u p/down cou n t er . Da t a la t ch Wh en LTn =1, t h e va lu e of u p/down cou n t er is st or ed in t o t h e la t ch r egist er . Con t r ol u n iver sa l ou t pu t 2 : wh en OCn 2(D7)=0 (com m a n d r egist er ) 0 : On 2="L" 1: ="H " Con t r ol u n iver sa l ou t pu t 1 : wh en OCn 1(D6)=0 (com m a n d r egist er ) 0 : On 1="L" 1: ="H "
D14
RLTn
D13
RAIn
D12
RCn
D11
RE n 1
D10
RE n 0
D9 D8 D7
LDn LTn OTn 2
D6
OTn 1
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ZEN2041F
Bit Sym bol D5 OTn 0 Descr ipt ion Con t r ol u n iver sa l ou t pu t 0 : wh en OCn 0(D5)=0 (com m a n d r egist er ) 0 : On 0="L" 1: ="H " 0 equ a l t o D3 of m ode r egist er equ a l t o D2 of m ode r egist er 0 0
D4 D3 D2 D1 D0
ZE n 1 ZE n 0 -
7) Globa l com m a n d r egist er Ta ble.7 Bit Sym bol D15 LD3 D14 LD2 D13 LD1 D12 LD0 D11 LT3 D10 LT2 D9 LT1 D8 LT0 D7-D0 Descr ipt ion E qu a l t o D9 (com m a n d r egist er 3) D9 2 D9 1 D9 0 D8 3 D8 2 D8 1 D8 0 0
8) Mon it or r egist er : m on it or a ll in pu t sign a ls. Su bscr ipt n is 0 t o 3. Ta ble.8 : F or m a t of t h e m on it or r egist er n Bit Sym bol Descr ipt ion D15 P n 0M Mon it or P n 0 sign a l 0 : P n 0="L" 1: ="H " D14 P n 1M Mon it or P n 1 sign a l 0 : P n 1="L" 1: ="H " D13 Cn M Mon it or Cn sign a l 0 : Cn ="L" 1 : ="H " D12 LDn M Mon it or LDn sign a l 0 : LDn ="L" 1: ="H " D11 LTn M Mon it or LTn sign a l 0 : LTn ="L" 1: ="H " D10 MDn M Mon it or MDn sign a l 0 : MDn ="L" 1: ="H " D9 DIRn M Mon it or DIRn sign a l 0 : DIRn ="L" 1: ="H " D8 Sm M Mon it or Sm sign a l : is en a ble for t h e st a t u s r egist er 00 a n d 20. 0 : Sm ="L" 1 : ="H " D7-D0 fixed '0'
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ZEN2041F
9) St a t u s r egist er : Su bscr ipt n is 0 t o 3. Bit Sym bol D15 SILDn Ta ble.9 Descr ipt ion Don e in t er r u pt by LDn . Reset by RLDn (D15)=1 of t h e com m a n d r egist er n . 0 : not don e 1 : Don e Don e in t er r u pt by LTn . Reset by RLTn (D14)=1 of t h e com m a n d r egist er n . 0 : n ot don e 1 : Don e Don e in t er r u pt by a bn or m a l in pu t . Reset by RAIn (D13)=1 of t h e com m a n d r egist er n . 0 : n ot don e 1 : Don e Don e in t er r u pt by Cn . Reset by ICn (D12)=1 of t h e com m a n d r egist er n . 0 : n ot don e 1 : Don e Don e in t er r u pt by coin ciden ce det ect ion . Reset by RE n 1(D11)=1 of t h e com m a n d 0 : n ot don e r egist er n . 1 : Don e Don e in t er r u pt by coin ciden ce det ect ion . Reset by RE n 0(D10)=1 of t h e com m a n d 0 : n ot don e r egist er n . 1 : Don e Com plet ed loa din g da t a 0 : r eset a ft er r ea din g ou t . 1 : is set wit h com plet ion of st or in g t h e loa d r esist er va lu e in t o t h e cou n t er . Com plet ed la t ch in g da t a 0 : r eset a ft er r ea din g ou t . 1 : is set wit h com plet ion of st or in g t h e cou n t er va lu e in t o t h e la t ch r egist er Mon it or E P n : equ a l t o E P n Mon it or E n 1 : equ a l t o E n 1 Mon it or E n 0 : equ a l t o E n 0 0 In dica t e t o don e in t er r u pt 0 : N ot don e 1 : Don e
D14
SILTn
D13
SAIn
D12
SCn
D11
SE n 1
D10
SE n 0
D9
SLDn
D8
SLTn
D7 D6 D5 D4 D3 D2 D1 D0
EPnM E n 1M E n 0M ISR3 ISR2 ISR1 ISR0
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ZEN2041F
8. Counter operation and Timing Th ese sign a ls a r e sa m pled by CLK. RE SE T, P u lse in pu t (P 00-P 31), Clea r (C0-C3), Loa d da t a (LD0-LD3), La t ch da t a (LT0-LT3) 1) Cou n t in g oper a t ion Ta ble.10 Cou n t in g dir ect ion P h a se-sh ift ed pu lse (MDn ="L") DIRn P h a se Cou n t in g dir ect ion 1 Pn0 phase 90 advance Cou n t u p Pn1 phase 90 advance Cou n t down 0 Pn0 phase 90 advance Cou n t down Pn1 phase 90 advance Cou n t u p U p/down pu lse (MDn ="H ") DIRn Risin g edge 1 Pn0 Pn1 0 Pn0 Pn1
Cou n t in g dir ect ion Cou n t u p Cou n t down Cou n t down Cou n t u p
2) Cou n t t im in g ( Refer t o F igu r e.3-1 ) P h a se-sh ift ed pu lse Cou n t in g con dit ion is depen d on t h e edge eva lu a t ion . E dge eva lu a t ion Cou n t in g con dit ion sin gle Ch a n ge of P n 0 wh en P n 1="L" dou ble Ch a n ge of P n 0 qu a d Ch a n ge of P n 0 or P n 1 U p/down pu lse Wh en it is sa m pled t h e r isin g edge of pu lse in pu t , cou n t u p or down depen d on DIRn . Don 't ch a n ge t h e ot h er in pu t . 3) Abn or m a l in pu t P h a se-sh ift ed pu lse Th e defin it ion of a bn or m a l in pu t is t h e sim u lt a n eou sly ch a n gin g P n 0 wit h P n 1. Ca u ses of a bn or m a l in pu t * It ca n n ot be sa m pled beca u se t h e ch a n gin g t im e of in pu t is t oo sh or t . * t h e t r a n sit ion st a t e is a bn or m a l beca u se t h e n oise is sa m pled. U p/down pu lse N o defin it ion 4) Clea r oper a t ion : Refer t o F igu r e.3-2. * Asyn ch r on ou s clea r Aft er t h e r isin g edge of Cn is det ect ed, t h e cou n t er is clea r ed. * Syn ch r on ou s clea r Aft er Cn ="H ",P n 1="L",a n d ch a n ge of P n 0 a r e det ect ed, t h e cou n t er is clea r ed. 5) Loa din g da t a , La t ch in g da t a oper a t ion : Refer t o F igu r e.3-3. (Z2041B98)ZENIC Inc. - 11 -
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ZEN2041F
F igu r e.3-1 : Cou n t in g oper a t ion P h a se-sh ift ed pu lse in pu t ( DIRn ="H " ) CLK Pn0 Pn1
CN Tn x4 CN Tn x2 CN Tn x1
M
M+1 M+2 M+3 M+4 M+3 M+2 M+1
M
M
M+1
M+2
M+1
M
M
M+1
M
If IAIn =1(D13 of m ode r egist er ) IN T
U p/down pu lse in pu t ( DIRn ="H " )
CLK Pn0 Pn1
CN Tn
M
M+1
M
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ZEN2041F
F igu r e.3-2 : Clea r in g Oper a t ion * Asyn ch r on ou s clea r in g CLK Cn CN Tn Cou n t in g Oper a t ion 0000H If ICn =1 (D12 of m ode r egist er ) IN T * Syn ch r on ou s clea r in g ( on ly for ph a se-sh ift ed pu lse in pu t ) St a r t cou n t
CLK Pn0 Pn1 Cn CN Tn Cou n t in g oper a t ion 0000H If ICn =1 (D12 of m ode r egist er ) IN T St a r t cou n t "H " "L" or "L" "H "
F igu r e.3-3 : Loa din g da t a , La t ch in g da t a
CLK LDn LTn CN Tn LTRn L N M( Loa d r egist er n = "M" ) M
If ILDn =1 (D15 of m ode r egist er ) IN T If ILTn =1 (D14 of m ode r egist er ) IN T
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ZEN2041F
9. Coincidence Detection Th er e a r e t wo r efer en ce r egist er s for ever y cou n t er . Th ey a r e u sed for st or in g da t a t o win dow com pa r ison . An d it ou t pu t s a coin ciden ce sign a l a r efer en ce r egist er wit h cou n t va lu e. 1) In depen den t ( S0,S1="L" ) U p/down L o w e r Cou n t er va lu e r egist er CN T0 CMR00 CN T1 CN T2 CN T3 CMR10 CMR11 CMR20 CMR21 CMR30 CMR31 Coin ciden ce sign a l is "L" du r in g Upper va lu e r egist er CMR01 Ta ble.12 Coin ciden ce Win dow sign a l ou t pu t E 00 EP0 E 01 E 10 EP1 E 11 E 20 EP2 E 21 E 30 EP3 E 31 cou n t va lu e=r efer en ce r egist er .
Win dow ou t pu t is "L" Con dit ion 1 : lower va lu e r egist er < u pper va lu e r egist er , Du r in g : lower va lu e r egist er < cou n t va lu e < u pper va lu e r egist er Con dit ion 2 : lower va lu e r egist er = u pper va lu e r egist er , Du r in g : cou n t va lu e = lower va lu e r egist er Con dit ion 3 : lower va lu e r egist er > u pper va lu e r egist er , Du r in g : cou n t va lu e = lower va lu e r egist er or u pper va lu e r egist er 2) Ca sca de con n ect ( S0,S1="H " ) Ta ble.13 cou n t er lower va lu e r egist er u pper va lu e r egist er coin ciden ce win dow lower wor d u pper wor d lower wor d u pper wor d lower wor d u pper wor d sign a l ou t pu t CN T0 CN T1 CMR00 CMR10 E 10 EP1 CMR01 CMR11 E 11 CN T2 CN T3 CMR20 CMR30 E 30 EP3 CMR21 CMR31 E 31
cou n t va lu e = (cou n t er u pper wor d)*10000(H ) + (cou n t er lower wor d) lower va lu e r egist er = (u pper wor d r egist er )*10000(H ) + (lower wor d r egist er ) u pper va lu e r egist er = (u pper wor d r egist er )*10000(H ) + (lower wor d r egist er ) N ot e If en a ble in t er r u pt , wh ile cou n t er va lu e equ a l t o r efer en ce r egist er , in t er r u pt ou t pu t is "Low". E xa m ple of in t er r u pt pr ocess. 1, u n a ble in t er r u pt or m odify r efer en ce r egist er . 2, r eset in t er r u pt . 3, in t er r u pt pr ocess. 4, exit in t er r u pt r ou t in e. 5, if cou n t er va lu e u n equ a l t o r efer en ce r egist er , en a ble in t er r u pt .
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ZEN2041F
F igu r e.4 : Coin ciden ce det ect ion a n d win dow ou t pu t Wh en a r efer en ce r egist er n 0 = "L" a n d a r efer en ce r egist er n 1 = "M" CLK CN Tn En0 En1 EPn If IE n 0=1 (D10 of m ode r egist er n ) IN T If IE n 1=1 (D11 of m ode r egist er n ) IN T 10. Electrical specification 1) Absolu t e m a xim u m r a t in g Ra t in g Sym bol Su pply volt a ge VDD In pu t volt a ge VI Ou t pu t volt a ge VO In pu t cu r r en t II St or a ge t em per a t u r e T STG Min . VSS-0.5 VSS-0.5 VSS-0.5 -20 -50 Ma x. VSS+7.0 VDD+0.5 VDD+0.5 +20 +125 U n it V V V mA C
L-1 L L+1 M-1 M M+1
2) Recom m en ded oper a t in g con dit ion s Ra t in g Sym bol Su pply volt a ge VDD Oper a t in g t em per a t u r e T OP Min . 4.50 -40 Typ. 5.00 25
VSS=0V Ma x. U n it 5.50 V +70 C
3) DC ch a r a ct er ist ics ( a t t h e r ecom m en ded oper a t in g con dit ion s ) Ra t in g In pu t "H " level volt a ge "L" Ou t pu t "H " volt a ge "L" In pu t lea ka ge cu r r en t St a n dby cu r r en t Sym bol Con dit ion s VIH TTL in pu t VIL TTL in pu t VOH I OH = -4m A VOL I OL=4m A IL VI=VDD/VSS I DDS VIH = VDD,VIL= VSS Min . 2.2 VDD-1.0 -10 Typ. Ma x. 0.8 VSS+0.4 +10 100 U n it V V V V A A
4) AC ch a r a ct er ist ics-1 ( a t t h e r ecom m en ded oper a t in g con dit ion s ) N O. Sym bol Ra t in g 1 R Risin g u p t im e of CLK 2 F F a llin g down t im e of CLK 4.5(V) 0.5(V) 1 Min . Ma x. U n it 5 ns 5 ns
CLK
4.5(V) 0.5(V) 2 (Z2041B98)ZENIC Inc. - 15 -
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ZEN2041F
5) AC ch a r a ct er ist ics -2 ( n =0 ~ 3, a t t h e r ecom m en ded oper a t in g con dit ion s ) N O. Sym bol 1 CY CLK Cycle 2 H CLK P u lse 3 L CLK P u lse 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 TWAS TWAH TWRL TWRH TDS TDH TRAS TRAH TRDL TRDH TZV TDZ T 10 T 01 T S10 T H10 T S01 T H01 T PW T CW T LW TRL TRH Ra t in g t im e widt h ("H igh ") widt h ("Low") Min . 50 25 25 5 5 100 5 CY 40 0 5 5 100 4 CY 70 70 CY+ 25 CY+ 25 CY+ 25 CY+ 25 CY+ 25 CY+ 25 CY+ 25 CY+ 25 CY+ 25 5 CY 5 CY 65 40 Ma x. U n it ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Set t in g u p t im e of a ddr ess for WR H oldin g t im e of a ddr ess for WR - WR pu lse widt h ("Low") Recover in g t im e a ft er r isin g u p WR(n ot e.3) Set t in g u p t im e of in pu t da t a for WR - H oldin g t im e of in pu t da t a for WR - Set t in g u p t im e of a ddr ess for RD H oldin g t im e of a ddr ess for RD - RD pu lse widt h ("Low") Recover in g t im e a ft er r isin g u p RD(n ot e.3) Deley t im e fr om RD t o fixed da t a Deley t im e fr om RD - t o floa t ou t pu t Set t in g u p t im e of P n 0 for P n 1 Set t in g u p t im e of P n 1 for P n 0 Set t in g u p t im e of P n 0 for P n 1 - H oldin g t im e of P n 0 for P n 1 - Set t in g u p t im e of P n 1 for P n 0 - H oldin g t im e of P n 1 for P n 0 - P u lse widt h of in pu t (P n 0,P n 1) P u lse widt h of Cn P u lse widt h of LDn ,LTn P u lse widt h of RE SE T Recover in g t im e a ft er r isin g u p RE SE T
27 TI Dela y t im e fr om CLK - t o IN T ou t pu t 28 TE Dela y t im e fr om CLK - t o coin ciden ce ou t pu t n ot e.3) In h ibit t im e t o r ea d or wr it e. Mea su r in g con dit ion for AC ch a r a ct er ist ics -2 Ra t in g Sym bol St a n da r d va lu e U n it In pu t dr ivin g level VIH 2.4 (3.0) V VIL 0.45(0.4) V Test poin t of t im in g VOH 2.0 V (in pu t ,ou t pu t ) VOL 0.8 V Loa din g ca pa cit y CL 50 pF Loa din g cu r r en t I OH -4 mA I OL 4 mA Th e va lu e in pa r en t h eses is for CLK in pu t . Oper a t ion cu r r en t Ra t in g Oper a t ion cu r r en t
Sym bol Mea su r in g con dit ion Max U n it I DDO Ou t pu t is open 90 mA CLK = 20MH z (Z2041B98)ZENIC Inc. - 16 -
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Tim in g dia gr a m Clock 1 CLK 2 3
Wr it e cycle ( W/B="H " or "L" ) Addr ess* 4 WR 6 D0 ~ D15 8 9 7 5
Rea d cycle ( W/B="H " or "L" ) Addr ess* 10 RD 12 D0 ~ D15 14 15 13 11
*Addr ess : CS, AD5 ~ AD0, BH E
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ZEN2041F
In pu t t im in g P h a se -sh ift ed pu lse in pu t Pn0
Pn1 16 17
U p/down pu lse in pu t Pn0
Pn1 18 22 19 22
Pn1
Pn0 20 22 21 22
Cn 23 LDn LTn CS RE SE T 25 26 23
24
24
Ou t pu t t im in g CLK 27 IN T 28 Coin ciden ce ou t pu t *Coin ciden ce ou t pu t : E 00/O00,E 01/O01,E 10/O10,E 11/O11 E 20/O20,E 21/O21,E 30/O30,E 31/O31 E P 0/O02,E P 1/O12,E P 2/O22,E P 3/O32 (Z2041B98)ZENIC Inc. - 18 -
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11. Package outlines ( Dimensions in mm )
24 . 80 } 0. 4 0 2 0. 0 0 } 0. 30 80 51 0. 15 } 0 . 0 5
81
50 14 . 0 0 } 0. 30 18 . 8 0 } 0. 40
100
31
2. 75 } 0 . 20
1 P- 0 . 65 TYP
30 0 . 3 0 } 0. 10
( 2. 40 ) 0 - 15 1. 20 } 0. 20 0 . 2 0 } 0. 20
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ZENIC r eser ves t h e r igh t t o m a k e ch a n ges in it s pr odu ct wit h ou t a n y n ot ice t o im pr ove r elia bilit y, fu n ct ion or design . ZENIC does n ot a ssu m e a n y lia bilit y a r isin g ou t of t h e a pplica t ion or u se of a n y pr odu ct or cir cu it descr ibed h er ein ;n eit h er does it con vey a n y licen se u n der it s pa t en t r igh t s n or t h e r igh t s of ot h er s. In for m a t ion con t a in ed in t h is pu blica t ion r ega r din g device a pplica t ion s a n d t h e lik e is in t en ded t h r ou gh su ggest ion on ly a n d m a y be su per seded by u pda t es. ZENIC pr odu ct s a r e n ot design ed, in t en ded, or a u t h r ized for u se a s com pon en t s in syst em s in t en ded for su r gica l im pla n t in t o t h e body, or ot h er a pplica t ion s in t en ded t o su ppor t or su st a in life, or for a n y ot h er a pplica t ion in wh ich t h e fa ilu r e of t h e ZENIC pr odu ct s cou ld cr ea t e a sit u a t ion wh er e per son a l in ju r y or dea t h m a y occu r .
All r igh t r eser ved. Copyr igh t 1995, ZENIC INC.
ZENIC Inc.
U RL h t t p://www.zen ic.co.jp/ 1-17-14, Oh ga ya Oh t su Sh iga 520-2144, J AP AN F a x. +81-77-543-9431 E -m a il su ppor t @zen ic.co.jp (Z2041B98) ZENIC Inc. - 20 -

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